1. Field of the Invention
The present invention generally relates to the fabrication and design of semiconductor chips and integrated circuits, and more particularly to a method of designing the netlist connections of latches and other logic cells to improve radiation tolerance.
2. Description of the Related Art
Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches to the most complex computer systems. A microelectronic integrated circuit (IC) chip can generally be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate (e.g., silicon). An IC may include a very large number of cells and require complicated connections between the cells. A cell is a group of one or more circuit elements such as transistors, capacitors, resistors, inductors, and other basic circuit elements grouped to perform a logic function. Cell types include, for example, core cells, scan cells and input/output (I/O) cells. Each of the cells of an IC may have one or more pins, each of which in turn may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip. For more complex designs, there are typically at least four distinct layers of conducting media available for routing, such as a polysilicon layer and three metal layers (metal-1, metal-2, and metal-3). The polysilicon layer, metal-1, metal-2, and metal-3 are all used for vertical and/or horizontal routing.
An IC chip is fabricated by first conceiving the logical circuit description, and then converting that logical description into a physical description, or geometric layout. This process is usually carried out using a “netlist,” which is a record of all of the nets, or interconnections, between the cell pins. A layout typically consists of a set of planar geometric shapes in several layers. The layout is then checked to ensure that it meets all of the design requirements, particularly timing requirements. The result is a set of design files in an intermediate form that describe the layout. The design files are then converted into pattern generator files that are used to produce patterns called masks by an optical or electron beam pattern generator. During fabrication, these masks are used to pattern a silicon wafer using a sequence of photolithographic steps. The process of converting the specifications of a circuit into a layout is called the physical design.
Cell placement in semiconductor fabrication involves a determination of where particular cells should optimally (or near-optimally) be located on the surface of a integrated circuit device. Due to the large number of components and the details required by the fabrication process for very large scale integrated (VLSI) devices, physical design is not practical without the aid of computers. As a result, most phases of physical design extensively use computer-aided design (CAD) tools, and many phases have already been partially or fully automated. Automation of the physical design process has increased the level of integration, reduced turn around time and enhanced chip performance. Several different programming languages have been created for electronic design automation (EDA) including Verilog, VHDL and TDML. A typical EDA system receives one or more high level behavioral descriptions of an IC device, and translates this high level design language description into netlists of various levels of abstraction.
Placement algorithms are typically based on either a simulated annealing, top-down cut-based partitioning, or analytical paradigm (or some combination thereof). Analytical placers optimally solve a relaxed placement formulation, for example, minimizing total quadratic wire length. Placers can use other techniques to optimize circuit characteristics such as timing and power. One method involves the use of local clock buffers (LCBS) or clock splitters to distribute the clock signals. A typical clock control system has a clock generation circuit (e.g., a phase-lock loop) that generates a master clock signal which is fed to a clock distribution network that renders synchronized global clock signals at the LCBs. Each LCB adjusts the global clock duty cycle and edges to meet the requirements of respective circuit elements, such as local logic circuits or latches (the term “latch” as used herein stands for any clocked element, which is often a sink of a network). Clock splitters may be used to produce multiple clock signals having different phases.
Since clock networks can be one of the largest power consumers among all of the interconnects, it is further beneficial to control the capacitive load of the LCBs, each of which is driving a set of many clock sinks. One approach for reducing the capacitive load is latch clustering, i.e., clusters of latches placed near the respective LCB of their clock domain. Latch clustering combined with LCBs can significantly reduce the total clock wire capacitance which in turn reduces overall clock power consumption. Since most of the latches are placed close to an LCB, clock skew is also reduced which helps improve the timing of the circuit.
While these techniques provide adequate placement of cells with regard to their data interconnections, power and timing, there is an additional challenge for the designer in constructing a circuit that is resistant to soft errors, and this challenge is becoming more difficult with the latest technologies like 65-nanometer application-specific integrated circuits (ASICs). Soft errors are caused by, e.g., alpha particle strikes emitted from packaging materials or by neutrons originating from cosmic radiation. The soft-error rate (SER) of a data processing system can exceed the combined failure rate of all hard-reliability mechanisms (gate oxide breakdown, electro-migration, etc.). Radiation tolerance has thus become a necessity for meeting robustness targets in advanced systems. All storage elements (random-access memory, latches, etc.) are highly susceptible to soft-error induced failures, but memory arrays are usually protected by error-correction codes while latches are usually not so protected. Soft errors in ASIC logic book latches can accordingly be a major contributor to overall system SER.
Information stored in latches may include control, status or mode bits. For example, a data processing system might provide different mode configurations for clock control logic, and clock control latches can account for a significant portion of an ASIC latch count. These clock buffer modes are set at system power-on and often must maintain their logical value for days or months to ensure proper performance of the local logic circuits. However, the values can be upset during operation due to soft errors. An upset may be correctable by scanning in a new value, but systems may only allow input scanning in a limited manner such as at power-on, meaning that the system must be restarted if a clock control latch becomes incorrectly set. These reliability problems are particularly troublesome for harsher operating environments, such as aerospace systems where there is increased radiation (high-altitude or orbital space). Design parameters used to optimize circuits for terrestrial applications can actually be detrimental to radiation tolerance. Placers which try to minimize area will place many critical components closer to one another, making it more likely that a particle strike will cause multiple upsets.
Even if ASIC logic book data nets are hardened, upsets in the clock trees may still lead to logical upsets in the books, e.g., when an incorrect data value is captured at a latch due to a faulty clock signal. To make matters worse, ASIC logic books are designed with a single clock input. This clock input is shared among several ASIC logic books, so an upset in the clock signal can lead to multiple latches sampling incorrect data. It would, therefore, be desirable to devise an improved netlisting method which could take into account possible soft errors arising in the clock trees for critical components. It would be further advantageous if the method could be used in conjunction with existing EDA tools which provide other optimizations such as area, power and timing.